1. Field of the Invention
The present invention relates to a manufacturing method of semiconductor device that uses a sidewall double patterning technology (sidewall DPT).
Priority is claimed on Japanese Patent Application No. 2008-215609, filed Aug. 25, 2008, the content of which is incorporated herein by reference.
2. Description of Related Art
In the semiconductor device fabrication process, an optical projection exposure apparatus (hereinafter, referred to as an exposure apparatus) is broadly used as an apparatus for forming circuit patterns on a wafer. An exposure apparatus usually has therein a plurality of optical conditions, and the optical conditions are determined by the size, shape, and arrangement of the patterns to be exposed. For example, related illumination is used for sparse patterns having a lower integration level, whereas annular illumination is mainly used for dense patterns having a higher level of repetition as in the case of DRAM (dynamic random access memory) cells.
Moreover, with the trend of miniaturization and high performance of semiconductor devices, the patterns used on a circuit come in many and various forms. In related DRAM cells, patterns having an identical form that repeat at equal intervals were the mainstream patterns; however, many of the recent patterns lack repetitiveness, and hence, it is difficult to form a desired pattern by mere optimization of optical conditions.
When patterns lacking in repetitiveness are formed by an exposure apparatus, the light intensity distribution of the light transmitted through the pattern formed on a reticle becomes asymmetric with respect to the central line of the pattern. Therefore, the pattern formed on a wafer is likely to deviate from the position at which the pattern is to be formed.
When a trench gate pattern is formed on a Si substrate during the fabrication step of DRAMs having trench-gate MOS transistors, a positional deviation due to the asymmetric profile occurs.